POWER5 explained

POWER5 is a microprocessor developed and fabricated by IBM. It is an improved variant of the highly successful POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller. The POWER5 is a dual-core microprocessor, with each core supporting one physical thread and two logical threads, for a total of two physical threads and four logical threads.

The POWER5 die is packaged in either a dual chip module (DCM) or an multi-chip module (MCM). The DCM contains one POWER5 die and its associated L3 cache die, while the MCM contains four POWER5 dies and four L3 cache dies, one for each POWER5 die. The POWER5+ (presented in 3Q 2005) is packaged in a quad chip module (QCM) containing two POWER5+ dies and two L3 cache dies, one for each POWER5 die.

Several POWER5 processors in high-end systems can be coupled together to act as a single vector processor by a technology called ViVA (Virtual Vector Architecture).

IBM uses the POWER5 microprocessors in their System p and System i server families, their DS8000 storage server and as controllers in their high-end Infoprint printers.

Third-party users of the POWER5 are Groupe Bull, who uses them in their Escala servers, and Hitachi, who uses them in their SR11000 computers with up to 128 POWER5+ microprocessors, of which several installations are featured in the 2007 TOP500 list of supercomputers.

QCM support for IBM System p5 servers [1] :

See also

External links


  1. http://www.redbooks.ibm.com/redpapers/pdfs/redp4150.pdf