MOSFET explained

The metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET) is a device used to amplify or switch electronic signals. The basic principle of the device was first proposed by Julius Edgar Lilienfeld in 1925. It is by far the most common field-effect transistor in both digital and analog circuits.The MOSFET is composed of a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOS, pMOS).

Etymology

The 'metal' in the name is now often a misnomer because the previously metal gate material is now a layer of polysilicon (polycrystalline silicon; why polysilicon is used will be explained below). Previously aluminium was used as the gate material until the 1980s when polysilicon became dominant, owing to its capability to form self-aligned gates.

IGFET is a related, more general term meaning insulated-gate field-effect transistor, and is almost synonymous with MOSFET, though it can refer to FETs with a gate insulator that is not oxide. Some prefer to use "IGFET" when referring to devices with polysilicon gates, but most still call them MOSFETs.

Composition

Usually the semiconductor of choice is silicon, but some chip manufacturers, most notably IBM, have begun to use a mixture of silicon and germanium (SiGe) in MOSFET channels. Unfortunately, many semiconductors with better electrical properties than silicon, such as gallium arsenide, do not form good semiconductor-to-insulator interfaces and thus are not suitable for MOSFETs. However there continues to be research on how to create insulators with acceptable electrical characteristics on other semiconductor material.

To overcome power consumption increase due to gate current leakage, high-κ dielectric is replacing silicon dioxide as the gate insulator, and metal gates are making a comeback by replacing polysilicon (see Intel announcement[1]).

The gate is separated from the channel by a thin insulating layer of what was traditionally silicon dioxide, but more advanced technologies used silicon oxynitride. Some companies have started to introduce a high-κ dielectric + metal gate combination in the 45 nanometer node.

When a voltage is applied between the gate and source terminals, the electric field generated penetrates through the oxide and creates a so-called "inversion layer" or channel at the semiconductor-insulator interface. The inversion channel is of the same type – P-type or N-type – as the source and drain, so it provides a channel through which current can pass. Varying the voltage between the gate and body modulates the conductivity of this layer and makes it possible to control the current flow between drain and source.

Circuit symbols

A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used for enhancement mode and a solid line for depletion mode. Another line is drawn parallel to the channel for the gate.

The bulk connection, if shown, is shown connected to the back of the channel with an arrow indicating PMOS or NMOS. Arrows always point from P to N, so an NMOS (N-channel in P-well or P-substrate) has the arrow pointing in (from the bulk to the channel). If the bulk is connected to the source (as is generally the case with discrete devices) it is sometimes angled to meet up with the source leaving the transistor. If the bulk is not shown (as is often the case in IC design as they are generally common bulk) an inversion symbol is sometimes used to indicate PMOS, alternatively an arrow on the source (not depicted below) may be used in the same way as for bipolar transistors (out for NMOS, in for PMOS).

Comparison of enhancement-mode and depletion-mode MOSFET symbols, along with JFET symbols (Note, the 2nd and 4th columns of images should be flipped across y=0, so the higher voltages are above the lower voltages. The JFET symbols should be checked for correctness.):

P-channel
N-channel
JFETMOSFET enhMOSFET dep

For the symbols in which the bulk, or body, terminal is shown, it is here shown internally connected to the source. This is a typical configuration, but by no means the only important configuration. In general, the MOSFET is a four-terminal device, and in integrated circuits many of the MOSFETs share a body connection, not necessarily connected to the source terminals of all the transistors.

MOSFET operation

For the operation of MOS devices discussed next, an authoritative reference is Tsividis[2] .

Metal–oxide–semiconductor structure

A traditional metal–oxide–semiconductor (MOS) structure is obtained by depositing a layer of silicon dioxide (2) and a layer of metal (polycrystalline silicon is commonly used instead of metal) on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with

NA

the density of acceptors, p the density of holes; p = NA in neutral bulk), a positive voltage,

VGB

, from gate to body (see figure) creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions. See doping (semiconductor). If

VGB

is high enough, a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator. (Unlike the MOSFET, discussed below, where the inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers in the depletion region.) Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage.

This structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.

MOSFET structure and channel formation

A metal–oxide–semiconductor field-effect transistor (MOSFET) is based on the modulation of charge concentration by a MOS capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer which in the case of a MOSFET is an oxide, such as silicon dioxide. If dielectrics other than an oxide such as silicon dioxide (often referred to as oxide) are employed the device may be referred to as a metal–insulator–semiconductor FET (MISFET). The MOSFET includes two additional terminals (source and drain), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The highly doped source and drain regions typically are denoted by a '+' following the type of doping. The body is not highly doped, as denoted by the lack of a '+' sign.

If the MOSFET is an n-channel or nMOS FET, then the source and drain are 'n+' regions and the body is a 'p' region. As described above, with sufficient gate voltage, above a threshold voltage value, electrons from the source (and possibly also the drain) enter the inversion layer or n-channel at the interface between the p region and the oxide. This conducting channel extends between the source and the drain, and current is conducted through it when a voltage is applied between source and drain.

For gate voltages below the threshold value, the channel is lightly populated, and only a very small subthreshold leakage current can flow between the source and the drain.

If the MOSFET is a p-channel or pMOS FET, then the source and drain are 'p+' regions and the body is a 'n' region. When a negative gate-source voltage (positive source-gate) is applied, it creates a p-channel at the surface of the n region, analogous to the n-channel case, but with opposite polarities of charges and voltages. When a voltage less negative than the threshold value (a negative voltage for p-Channel) is applied between gate and source, the channel disappears and only a very small subthreshold current can flow between the source and the drain.

The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

The device may comprise a Silicon On Insulator (SOI) device in which a Buried OXide (BOX) is formed below a thin semiconductor layer. If the channel region between the gate dielectric and a Buried OXide (BOX) region is very thin, the very thin channel region is referred to as an Ultra Thin Channel (UTC) region with the source and drain regions formed on either side thereof in and/or above the thin semiconductor layer. Alternatively, the device may comprise a SEMiconductor On Insulator (SEMOI) device in which other semiconductors than silicon are employed. Many alternative semicondutor materials may be employed.

When the source and drain regions are formed above the channel in whole or in part, they are referred to as Raised Source/Drain RSD) regions.

Modes of operation

The operation of a MOSFET can be separated into three different modes, depending on the voltages at the terminals. In the following discussion, a simplified algebraic model is used that is accurate only for old technology. Modern MOSFET characteristics require computer models that have rather more complex behavior. For example, see Liu[3] and the device modeling list in http://www.designers-guide.org/links.html. For an enhancement-mode, n-channel MOSFET the three operational modes are:

Cut-off or Sub-threshold or Weak Inversion Mode
  • When VGS < Vth:
  • where

    Vth

    is the threshold voltage of the device.

    According to the basic threshold model, the transistor is turned off, and there is no conduction between drain and source. In reality, the Boltzmann distribution of electron energies allows some of the more energetic electrons at the source to enter the channel and flow to the drain, resulting in a subthreshold current that is an exponential function of gate–source voltage. While the current between drain and source should ideally be zero when the transistor is being used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold leakage.

    In weak inversion the current varies exponentially with gate-to-source bias

    VGS

    as given approximately by:[4] [5]

    IDID0e\begin{matrix

    VGS-Vth
    nVT

    \end{matrix}}

    ,

    where

    ID0

    = current at

    VGS=Vth

    and the slope factor n is given by

    n=1+CD/COX

    ,

    with

    CD

    = capacitance of the depletion layer and

    COX

    = capacitance of the oxide layer. In a long-channel device, there is no drain voltage dependence of the current once

    VDS>>VT

    , but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on). Frequently threshold voltage Vth for this mode is defined as the gate voltage at which a selected value of current ID0 occurs, for example, ID0 = 1 μA, which may not be the same Vth-value used in the equations for the following modes.

    Some micropower analog circuits are designed to take advantage of subthreshold conduction.[6] [7] [8] By working in the weak-inversion region, the MOSFETs in these circuits deliver the highest possible transconductance-to-current ratio, namely:

    gm/ID=1/(nVT)

    , almost that of a bipolar transistor. Unfortunately, bandwidth is low due to the low drive currents. Also, the subthreshold I-V relation depends exponentially upon threshold voltage, introducing a strong dependence on any manufacturing variation that affects threshold voltage; for example: variations in oxide thickness, junction depth, or body doping that change the degree of drain-induced barrier lowering. The resulting sensitivity to fabricational variations complicates optimization of circuits operating in the subthreshold mode.[9] [10]
    Triode Mode or Linear Region (also referred to as the Ohmic Mode[11] [12])
  • When VGS > Vth and VDS < (VGS - Vth)
  • The transistor is turned on, and a channel has been created which allows current to flow between the drain and source. The MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. The current from drain to source is modeled as:

    ID=\munCox

    W
    L

    \left((VGS-Vth)VDS-

    2
    V
    DS
    2

    \right)

    where

    \mun

    is the charge-carrier effective mobility,

    W

    is the gate width,

    L

    is the gate length and

    Cox

    is the gate oxide capacitance per unit area. The transition from the exponential subthreshold region to the triode region is not as sharp as the equations suggest.
    Saturation Mode (also referred to as the Active Mode[13] [14]):
  • When VGS > Vth and VDS > (VGS - Vth)
  • The switch is turned on, and a channel has been created, which allows current to flow between the drain and source. Since the drain voltage is higher than the gate voltage, the electrons spread out, and conduction is not through a narrow channel but through a broader, two- or three-dimensional current distribution extending away from the interface and deeper in the substrate. The onset of this region is also known as pinch-off to indicate the lack of channel region near the drain. The drain current is now weakly dependent upon drain voltage and controlled primarily by the gate–source voltage, and modeled very approximately as:

    ID=

    \munCox
    2
    W
    L

    (VGS-Vth)2\left(1+λVDS\right).

    The additional factor involving λ, the channel-length modulation parameter, models current dependence on drain voltage due to the Early effect, or channel length modulation. According to this equation, a key design parameter, the MOSFET transconductance is:

    gm=\begin{matrix}

    2ID
    VGS-Vth

    =

    2ID
    Vov

    \end{matrix}

    ,

    where the combination Vov = VGS - Vth is called the overdrive voltage.[15] Another key design parameter is the MOSFET output resistance

    rO

    given by:

    rO=\begin{matrix}

    1+λVDS
    λID

    \end{matrix}=\begin{matrix}

    1/λ+VDS
    ID

    \end{matrix}

    .

    If &lambda; is taken as zero, an infinite output resistance of the device results that leads to unrealistic circuit predictions, particularly in analog circuits.

    As the channel length becomes very short, these equations become quite inaccurate. New physical effects arise. For example, carrier transport in the active mode may become limited by velocity saturation. When velocity saturation dominates, the saturation drain current is more nearly linear than quadratic in VGS. At even shorter lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In addition, the output current is affected by drain-induced barrier lowering of the threshold voltage.

    Body effect

    The body effect describes the changes in the threshold voltage by the change in the source-bulk voltage, approximated by the following equation:

    VTN=VTO+\gamma\left(\sqrt{VSB+2\phi}-\sqrt{2\phi}\right)

    ,

    where

    VTN

    is the threshold voltage with substrate bias present, and

    VTO

    is the zero-

    VSB

    value of threshold voltage,

    \gamma

    is the body effect parameter, and

    2\phi

    is the surface potential parameter.

    The body can be operated as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect". [16]

    The primacy of MOSFETs

    In 1960, Ernesto Labate, Dawon Kahng and Martin M. (John) Atalla at Bell Labs invented the metal oxide semiconductor field-effect transistor (MOSFET).[17] Operationally and structurally different from the bipolar junction transistor,[18] the MOSFET was made by putting an insulating layer on the surface of the semiconductor and then placing a metallic gate electrode on that. It used crystalline silicon for the semiconductor and a thermally oxidized layer of silicon dioxide for the insulator. The silicon MOSFET did not generate localized electron traps at the interface between the silicon and its native oxide layer, and thus was inherently free from the trapping and scattering of carriers that had impeded the performance of earlier field-effect transistors. Following the (expensive) development of clean rooms to reduce contamination to levels never before thought necessary, and of photolithography[19] and the planar process to allow circuits to be made in very few steps, the

    Si-SiO2

    system possessed such technical attractions as low cost of production (on a per circuit basis) and ease of integration. Largely because of these two factors, the MOSFET has become the most widely used type of integrated circuit. A historical timeline of semiconductors can be found at computerhistory.org.

    CMOS circuits

    The principal reason for the success of the MOSFET was the development of digital CMOS logic,[20] which uses p- and n-channel MOSFETs as building blocks. Overheating is a major concern in integrated circuits since ever more transistors are packed into ever smaller chips. CMOS logic reduces power consumption because no current flows (ideally), and thus no power is consumed, except when the inputs to logic gates are being switched. CMOS accomplishes this current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct and a low voltage on the gates causes the reverse. During the switching time as the voltage goes from one state to another, both MOSFETs will conduct briefly. This arrangement greatly reduces power consumption and heat generation. Digital and analog CMOS applications are described below.

    Digital

    The growth of digital technologies like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor. A timeline can be found at computerhistory.org.[21] A big advantage of MOSFETs for digital switching is that the oxide layer between the gate and the channel prevents DC current from flowing through the gate, further reducing power consumption and giving a very large input impedance. The insulating oxide between the gate and channel effectively isolates a MOSFET in one logic stage from earlier and later stages, which allows a single MOSFET output to drive a considerable number of MOSFET inputs. Bipolar transistor-based logic (such as TTL) does not have such a high fanout capacity. This isolation also makes it easier for the designers to ignore to some extent loading effects between logic stages independently. That extent is defined by the operating frequency: as frequencies increase, the input impedance of the MOSFETs decreases.

    Analog

    The MOSFET's advantages in most digital circuits do not translate into supremacy in all analog circuits. The two types of circuit draw upon different features of transistor behavior. Digital circuits switch, spending most of their time outside the switching region, while analog circuits depend on MOSFET behavior held precisely in the switching region of operation. The bipolar junction transistor (BJT) has traditionally been the analog designer's transistor of choice, due largely to its higher transconductance and its higher output impedance (drain-voltage independence) in the switching region.

    Nevertheless, MOSFETs are widely used in many types of analog circuits because of certain advantages. The characteristics and performance of many analog circuits can be designed by changing the sizes (length and width) of the MOSFETs used. By comparison, in most bipolar transistors the size of the device does not significantly affect the performance. MOSFETs' ideal characteristics regarding gate current (zero) and drain-source offset voltage (zero) also make them nearly ideal switch elements, and also make switched capacitor analog circuits practical. In their linear region, MOSFETs can be used as precision resistors, which can have a much higher controlled resistance than BJTs. In high power circuits, MOSFETs sometimes have the advantage of not suffering from thermal runaway as BJTs do. Also, they can be formed into capacitors and gyrator circuits which allow op-amps made from them to appear as inductors, thereby allowing all of the normal analog devices, except for diodes (which can be made smaller than a MOSFET anyway), to be built entirely out of MOSFETs. This allows for complete analog circuits to be made on a silicon chip in a much smaller space.

    Some ICs combine analog and digital MOSFET circuitry on a single mixed-signal integrated circuit, making the needed board space even smaller. This creates a need to isolate the analog circuits from the digital circuits on a chip level, leading to the use of isolation rings and Silicon-On-Insulator (SOI). The main advantage of BJTs versus MOSFETs in the analog design process is the ability of BJTs to handle a larger current in a smaller space. Fabrication processes exist that incorporate BJTs and MOSFETs into a single device. Mixed-transistor devices are called Bi-FETs (Bipolar-FETs) if they contain just one BJT-FET and BiCMOS (bipolar-CMOS) if they contain complementary BJT-FETs. Such devices have the advantages of both insulated gates and higher current density.

    BJTs have some advantages over MOSFETs for at least two digital applications. Firstly, in high speed switching, they do not have the "larger" capacitance from the gate, which when multiplied by the resistance of the channel gives the intrinsic time constant of the process. The intrinsic time constant places a limit on the speed a MOSFET can operate at because higher frequency signals are filtered out. Widening the channel reduces the resistance of the channel, but increases the capacitance by the exact same amount. Reducing the width of the channel increases the resistance, but reduces the capacitance by the same amount. R*C=Tc1, 0.5R*2C=Tc1, 2R*0.5C=Tc1. There is no way to minimize the intrinsic time constant for a certain process. Different processes using different channel lengths, channel heights, gate thicknesses and materials will have different intrinsic time constants. This problem is mostly avoided with a BJT because it does not have a gate.

    The second application where BJTs have an advantage over MOSFETs stems from the first. When driving many other gates, called fanout, the resistance of the MOSFET is in series with the gate capacitances of the other FETs, creating a secondary time constant. Delay circuits use this fact to create a fixed signal delay by using a small CMOS device to send a signal to many other, many times larger CMOS devices. The secondary time constant can be minimized by increasing the driving FET's channel width to decrease its resistance and decreasing the channel widths of the FETs being driven, decreasing their capacitance. The drawback is that it increases the capacitance of the driving FET and increases the resistance of the FETs being driven, but usually these drawbacks are a minimal problem when compared to the timing problem. BJTs are better able to drive the other gates because they can output more current than MOSFETs, allowing for the FETs being driven to charge faster. Many chips use MOSFET inputs and BiCMOS (see above) outputs.

    MOSFET scaling

    Over the past decades, the MOSFET has continually been scaled down in size; typical MOSFET channel lengths were once several micrometres, but modern integrated circuits are incorporating MOSFETs with channel lengths of less than a tenth of a micrometre. Indeed Intel began production of a process featuring a 65 nm feature size (with the channel being even shorter) in early 2006. Until the late 1990s, this scaling resulted in great improvement in MOSFET circuit operation. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents, and lower output resistance, discussed below). The semiconductor industry maintains a "roadmap", the ITRS [22], describing forecasts and technology barriers to development for device sizes updated approximately annually. The 2006 roadmap[23] refers to devices with a physical gate length of 13 nm in size by the year 2013.

    Reasons for MOSFET scaling

    Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 2–3 years once a new technology node is introduced. For example the number of MOSFETs in a microprocessor fabricated in a 45 nm technology is twice as large as in a 65 nm chip. This doubling of the transistor count was first observed by Gordon Moore in 1965 and is commonly referred to as Moore's law.[24]

    It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the transistor length, width, and the oxide thickness, each (used to) scale with a factor of 0.7 per node. This way, the transistor channel resistance does not change with scaling, while gate capacitance is cut by a factor of 0.7. Hence, the RC delay of the transistor scales with a factor of 0.7.

    While this has been traditionally the case for the older technologies, for the state-of-the-art MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.

    Difficulties arising due to MOSFET size reduction

    Producing MOSFETs with channel lengths much smaller than a micrometre is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. In recent years, the small size of the MOSFET, below a few tens of nanometers, has created operational problems.

    Higher subthreshold conduction

    Because of small MOSFET geometries, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the "on" case and low current in the "off" case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips.[25] [26] [27]

    Increased gate-oxide leakage

    The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling occurs between the gate and channel, leading to increased power consumption.

    Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance. (Capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness.) All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant.

    Increased junction leakage

    To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, "halo" doping and so forth,[28] [29] all to decrease drain-induced barrier lowering. See also section on junction design. To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed,[30] increasing junction leakage. Heavier doping also is associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

    Lower output resistance

    For analog operation, good gain requires a high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the cascode and cascade amplifiers, or by feedback circuitry using operational amplifiers, for example a circuit like that in the adjacent figure.

    Lower transconductance

    The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance.

    Interconnect capacitance

    Traditionally switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the wires connecting different parts of the chip) is becoming a large percentage of capacitance.[31] [32] Signals have to travel through the interconnect, which leads to increased delay and lower performance.

    Heat production

    The ever-increasing density of MOSFETs on an integrated circuit is creating problems of substantial localized heat generation that can impair circuit operation. Circuits operate slower at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling methods are now required for many integrated circuits including microprocessors.

    Power MOSFETs are at risk of thermal runaway. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the heatsink is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device.

    Process variations

    With MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See design for manufacturability, reliability engineering, six sigma and statistical process control.[33]

    Modeling challenges

    Modern ICs are computer-simulated with the goal of obtaining working circuits from the very first manufactured lot. As devices are miniaturized, the complexity of the processing makes it difficult to predict exactly what the final devices look like, and modeling of physical processes becomes more challenging as well. In addition, microscopic variations in structure due simply to the probabilistic nature of atomic processes require statistical (not just deterministic) predictions. These factors combine to make adequate simulation and "right the first time" manufacture difficult.

    MOSFET construction

    Gate material

    The primary criterion for the gate material is that it is a good conductor. Highly-doped polycrystalline silicon is an acceptable, but certainly not ideal conductor, and it also suffers from some more technical deficiencies in its role as the standard gate material. Nevertheless, there are several reasons favoring use of polysilicon as a gate material:

    1. The threshold voltage (and consequently the drain to source on-current) is modified by the work function difference between the gate material and channel material. Because polysilicon is a semiconductor, its work function can be modulated by adjusting the type and level of doping. Furthermore, because polysilicon has the same bandgap as the underlying silicon channel, it is quite straightforward to tune the work function, so as to achieve low threshold voltages for both NMOS and PMOS devices. By contrast the work functions of metals are not easily modulated, so tuning the work function to obtain low threshold voltages becomes a significant challenge. Additionally, obtaining low threshold devices on both PMOS and NMOS devices would likely require the use of different metals for each device type, introducing additional complexity to the fabrication process.
    2. The Silicon-SiO2 interface has been well studied and is known to have relatively few defects. By contrast many metal–insulator interfaces contain significant levels of defects which can lead to fermi-level pinning, charging, or other phenomena that ultimately degrade device performance.
    3. In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better performing transistors. Such high temperature steps would melt some metals, limiting the types of metals that could be used in a metal-gate based process.

    While polysilicon gates have been the defacto standard for the last twenty years, they do have some disadvantages, which have led to the announcement of their replacement by metal gates. These disadvantages include:

    1. Polysilicon is not a great conductor (approximately 1000 times more resistive than metals) which reduces the signal propagation speed through the material. The resistivity can be lowered by increasing the level of doping, but even highly doped polysilicon is not as conductive as most metals. In order to improve conductivity further, sometimes a high temperature metal such as tungsten, titanium, cobalt, and more recently nickel, is alloyed with the top layers of the polysilicon. Such a blended material is called silicide. The silicide-polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing. Also the threshold voltage is not significantly higher than polysilicon alone, because the silicide material is not near the channel. The process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide, self-aligned silicide.
    2. When the transistors are extremely scaled down, it is necessary to make the gate dielectric layer very thin, around 1 nm in state-of-the-art technologies. A phenomenon observed here is the so-called poly depletion, where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion. To avoid this problem a metal gate is desired. A variety of metal gates such as tantalum, tungsten, tantalum nitride, and titanium nitride are used, usually in conjunction with high-k dielectrics. An alternative is to use fully-silicided polysilicon gates, and the process is referred to as FUSI.

    Insulator

    As devices are made smaller, insulating layers are made thinner, and at some point tunneling of carriers through the insulator from the channel to the gate electrode takes place. To reduce the resulting leakage current, the insulator can be made thicker by choosing a material with a higher dielectric constant. To see how thickness and dielectric constant are related, note that Gauss' law connects field to charge as:

    Q=\kappa{\epsilon}0E

    ,

    with Q = charge density, κ = dielectric constant, ε0 = permittivity of empty space and E = electric field. From this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased. The voltage on the gate is given by:

    VG=Vch+Etins=Vch+

    Qtins
    \kappa{\epsilon

    0}

    ,

    with VG = gate voltage, Vch = voltage at channel side of insulator, and tins = insulator thickness. This equation shows the gate voltage will not increase when the insulator thickness increases, provided κ increases to keep tins /κ = constant. See the article on high-κ dielectrics for more detail, and the section in this article on gate-oxide leakage.

    The insulator in a MOSFET is a dielectric which can in any event be silicon oxide, but many other dielectric materials are employed. The generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the MOSFET.

    Junction design

    The source-to-body and drain-to-body junctions are the object of much attention because of three major factors: their design affects the current-voltage (I-V) characteristics of the device, lowering output resistance, and also the speed of the device through the loading effect of the junction capacitances, and finally, the component of stand-by power dissipation due to junction leakage. The drain induced barrier lowering of the threshold voltage and channel length modulation effects upon I-V curves are reduced by using shallow junction extensions. In addition, halo doping can be used, that is, the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions.[34]

    The capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon.[35]

    These various features of junction design are shown (with artistic license) in the figure.

    Junction leakage is discussed further in the section increased junction leakage.

    Other MOSFET types

    Dual gate MOSFET

    The dual gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small signal devices in radio frequency applications where the second gate is normally used for gain control or mixing and frequency conversion.

    FinFET

    The Finfet, see figure to right, is a double gate device, one of a number of geometries being introduced to mitigate the effects of short channels and reduce drain-induced barrier lowering.

    Depletion-mode MOSFETs

    There are depletion-mode MOSFET devices, which are less commonly used than the standard enhancement-mode devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. In order to control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to a normally closed (on) switch, while the enhancement-mode device is equivalent to a normally open (off) switch.http://www.techweb.com/encyclopedia/imageFriendly.jhtml;?term=depletion+mode

    Due to their low noise figure in the RF region, and better gain, these devices are often preferred to bipolars in RF front-ends such as in TV sets. Depletion-mode MOSFET families include BF 960 by Siemens and BF 980 by Philips (dated 1980s), whose derivatives are still used in AGC and RF mixer front-ends.

    NMOS logic

    n-channel MOSFETs are smaller than p-channel MOSFETs and producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of NMOS logic which uses n-channel MOSFETs exclusively. However, unlike CMOS logic, NMOS logic consumes power even when no switching is taking place. With advances in technology, CMOS logic displaced NMOS logic in the 1980s to become the preferred process for digital chips.

    Power MOSFET

    See main article: Power MOSFET.

    Power MOSFETs have a different structure than the one presented above.[36] As with all power devices, the structure is vertical and not planar. Using a vertical structure, it is possible for the transistor to sustain both high blocking voltage and high current. The voltage rating of the transistor is a function of the doping and thickness of the N epitaxial layer (see cross section), while the current rating is a function of the channel width (the wider the channel, the higher the current). In a planar structure, the current and breakdown voltage ratings are both a function of the channel dimensions (respectively width and length of the channel), resulting in inefficient use of the "silicon estate". With the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness (actually the N-epitaxial layer thickness) is proportional to the breakdown voltage.

    It is worth noting that power MOSFETs with lateral structure are mainly used in high-end audio amplifiers. Their advantage is a better behaviour in the saturated region (corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical MOSFETs are designed for switching applications.

    DMOS

    DMOS stands for double-Diffused Metal Oxide Semiconductor. Most of the power MOSFETs are made using this technology.

    MOSFET analog switch

    MOSFET analog switches use the MOSFET channel as a low–on-resistance switch to pass analog signals when on, and as a high impedance when off. Signals flow in both directions across a MOSFET switch. In this application the drain and source of a MOSFET exchange places depending on the voltages of each electrode compared to that of the gate. For a simple MOSFET without an integrated diode, the source is the more negative side for an N-MOS or the more positive side for a P-MOS. All of these switches are limited on what signals they can pass or stop by their gate-source, gate-drain and source-drain voltages, and source-to-drain currents; exceeding the voltage limits will potentially damage the switch.

    Single-type MOSFET switch

    This analog switch uses a four-terminal simple MOSFET of either P or N type. In the case of an N-type switch, the body is connected to the most negative supply (usually GND) and the gate is used as the switch control. Whenever the gate voltage exceeds the source voltage by at least a threshold voltage, the MOSFET conducts. The higher the voltage, the more the MOSFET can conduct. An N-MOS switch passes all voltages less than (Vgate–Vtn). When the switch is conducting, it typically operates in the linear (or Ohmic) mode of operation, since the source and drain voltages will typically be nearly equal.

    In the case of a P-MOS, the body is connected to the most positive voltage, and the gate is brought to a lower potential to turn the switch on. The P-MOS switch passes all voltages higher than (Vgate+Vtp). Threshold voltage (Vtp) is typically negative in the case of P-MOS.

    A P-MOS switch will have about three times the resistance of an N-MOS device of equal dimensions because electrons have about three times the mobility of holes in silicon.

    Dual-type (CMOS) MOSFET switch

    See main article: Transmission gate.

    This "complementary" or CMOS type of switch uses one P-MOS and one N-MOS FET to counteract the limitations of the single-type switch. The FETs have their drains and sources connected in parallel, the body of the P-MOS is connected to the high potential (VDD) and the body of the N-MOS is connected to the low potential (Gnd). To turn the switch on the gate of the P-MOS is driven to the low potential and the gate of the N-MOS is driven to the high potential. For voltages between (VDD–Vtn) and (Gnd+Vtp) both FETs conduct the signal, for voltages less than (Gnd+Vtp) the N-MOS conducts alone and for voltages greater than (VDD–Vtn) the P-MOS conducts alone.

    The only limits for this switch are the gate-source, gate-drain and source-drain voltage limits for both FETs. Also, the P-MOS is typically three times the width of the N-MOS so the switch will be balanced.

    Tri-state circuitry sometimes incorporates a CMOS MOSFET switch on its output to provide for a low ohmic, full range output when on and a high ohmic, mid level signal when off.

    See also

    External links

    Notes and References

    1. Web site: Intel 45nm Hi-k Silicon Technology.
    2. Book: Yannis Tsividis. Operation and Modeling of the MOS Transistor. 1999. Second Edition. McGraw-Hill. New York. 0-07-065523-5.
    3. Book: William Liu. MOSFET Models for SPICE Simulation. 2001. Wiley-Interscience. New York. 0-471-39697-4.
    4. Book: P R Gray, P J Hurst, S H Lewis, and R G Meyer. Analysis and Design of Analog Integrated Circuits. 2001. 66-67. Fourth Edition. Wiley. New York. 0-471-32168-0.
    5. Book: P. R. van der Meer, A. van Staveren, A. H. M. van Roermund. Low-Power Deep Sub-Micron CMOS Logic: Subthreshold Current Reduction. 2004. 78. Springer. Dordrecht. 1402028482.
    6. Book: Leslie S. Smith, Alister Hamilton. Neuromorphic Systems: Engineering Silicon from Neurobiology. 1998. 52-56. World Scientific. 9810233779.
    7. Book: Satish Kumar. Neural Networks: A Classroom Approach. 2004. 688. Tata McGraw-Hill. 0070482926.
    8. Book: Manfred Glesner, Peter Zipf, Michel Renovell. Field-programmable Logic and Applications: 12th International Conference. 2002. 425. Dordrecht. Springer. 3540441085.
    9. Book: Sandeep K. Shukla, R. Iris Bahar. Nano, Quantum and Molecular Computing. 2004. 10 and Fig. 1.4, p. 11. Springer. 1402080670.
    10. Book: Ashish Srivastava, Dennis Sylvester, David Blaauw. Statistical Analysis and Optimization For VLSI: Timing and Power. 2005. 135. Springer. 0387257381.
    11. Book: C Galup-Montoro & Schneider MC. MOSFET modeling for circuit analysis and design. 2007. 83. World Scientific. London/Singapore. 981-256-810-7.
    12. Book: Norbert R Malik. Electronic circuits: analysis, simulation, and design. 1995. 315–316. Prentice Hall. Englewood Cliffs, NJ. 0-02-374910-5.
    13. Book: PR Gray, PJ Hurst, SH Lewis & RG Meyer. §1.5.2 p. 45. 0-471-32168-0.
    14. Book: A. S. Sedra and K.C. Smith. Microelectronic circuits. 2004. Fifth Edition. 552. Oxford. New York. 0-19-514251-9.
    15. Book: A. S. Sedra and K.C. Smith. p. 250, Eq. 4.14. 0-19-514251-9.
    16. http://equars.com/~marco/poli/phd/node20.html Body effect
    17. U.S. Patent 3,102,230 (filed in 1960, issued in 1963) http://www.computerhistory.org/semiconductor/timeline/1960-MOS.html
    18. http://www.computerhistory.org/semiconductor/timeline/1948-conception.html Computer History Museum - The Silicon Engine | 1948 - Conception of the Junction Transistor
    19. http://www.computerhistory.org/semiconductor/timeline/1955-Photolithography.html Computer History Museum - The Silicon Engine | 1955 - Photolithography Techniques Are Used to Make Silicon Devices
    20. http://www.computerhistory.org/semiconductor/timeline/1963-CMOS.html Computer History Museum - The Silicon Engine | 1963 - Complementary MOS Circuit Configuration is Invented
    21. http://www.computerhistory.org/microprocessors/ Computer History Museum - Exhibits - Microprocessors
    22. Web site: International Technology Roadmap for Semiconductors.
    23. Web site: Process Integration, Devices, and Structures. International Technology Roadmap for Semiconductors: 2006 Update.
    24. Web site: 1965 – “Moore's Law” Predicts the Future of Integrated Circuits. Computer History Museum.
    25. Book: Kaushik Roy, Kiat Seng Yeo. Low Voltage, Low Power VLSI Subsystems. 2004. Fig. 2.1, p. 44. McGraw-Hill Professional. 007143786X. true.
    26. Book: Kaushik Roy, Kiat Seng Yeo. Low Voltage, Low Power VLSI Subsystems. 2004. Fig. 1.1, p. 4. McGraw-Hill Professional. 007143786X. true.
    27. Book: Dragica Vasileska, Stephen Goodnick. Computational Electronics. 2006. 103. Morgan & Claypool. 1598290568.
    28. http://frontiersemi.com/pdf/papers/RsLransist.pdf Frontier Semiconductor Paper
    29. Book: Wai-Kai Chen. The VLSI Handbook. Fig. 2.28, p. 2-22. 2006. CRC Press. 084934199X. true.
    30. A Comparison Of Spike, Flash, Sper and Laser Annealing For 45nm CMOS: http://www.mrs.org/s_mrs/sec_subscribe.asp?CID=2593&DID=109911&action=detail
    31. VLSI wiring capacitance http://www.research.ibm.com/journal/rd/293/ibmrd2903G.pdf
    32. Book: D Soudris, P Pirsch, E Barke (Editors). Integrated Circuit Design: Power and Timing Modeling, Optimization, and Simulation (10th Int. Workshop). 2000. 38. Springer. 3540410686.
    33. Book: Michael Orshansky, Sani Nassif, Duane Boning. Design for Manufacturability And Statistical Design: A Constructive Approach. 2007. Springer. New York 309284.
    34. Book: Jean-Pierre Colinge, Cynthia A. Colinge. Physics of Semiconductor Devices. 2002. 233, Figure 7.46. Springer. Dordrecht. 1402070187.
    35. Book: Eicke R. Weber, Jarek Dabrowski (Editors). Predictive Simulation of Semiconductor Processing: Status and Challenges. 2004. 5, Figure 1.2. Springer. Dordrecht. 3540204814.
    36. Power Semiconductor Devices, B. Jayant Baliga, PWS publishing Company, Boston. ISBN 0-534-94098-6