AMD Turion is the brand name AMD applies to its 64-bit low-power consumption (mobile) processors codenamed K8L. The Turion 64 and Turion 64 X2/Ultra processors compete with Intel's mobile processors, initially the Pentium M and the Intel Core and Intel Core 2 processors.
Earlier Turion 64 processors are compatible with AMD's Socket 754. The newer "Richmond" models are designed for AMD's Socket S1. They are equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die DDR-400 memory controller, and an 800 MHz HyperTransport bus. Battery saving features, like PowerNow!, are central to the marketing and usefulness of these CPUs.
|solo (90 nm)|
solo (90 nm)
solo (65 nm)
|dual (90 nm)|
dual (90 nm)
dual (65 nm)
dual (65 nm)
|Lion||dual (65 nm)||Jun 2008|
|Caspian||dual (45 nm)||Sep 2009|
|Champlain||dual (45 nm)||May 2010|
See also: List of AMD Turion microprocessors.
Turion 64 X2 is AMD's 64-bit dual-core mobile CPU, intended to compete with Intel's Core and Core 2 CPUs. The Turion 64 X2 was launched on May 17, 2006, after several delays. These processors use Socket S1, and feature DDR2 memory. They also include AMD Virtualization Technology and more power-saving features.
AMD first produced the Turion 64 X2 on IBM's 90 nm Silicon on insulator (SOI) process (cores with the Taylor codename). As of May 2007, they have switched to a 65 nm Silicon-Germanium stressed process, which was recently achieved through the combined effort of IBM and AMD, with 40% improvement over comparable 65 nm processes. The earlier 90 nm devices were codenamed Taylor and Trinidad, while the newer 65 nm cores have codename Tyler.
Turion X2 Ultra (codenamed Griffin) is the first processor family from AMD solely for the mobile platform, based on the Athlon 64 (K8 Revision G) architecture with some specific architectural enhancements similar to current Phenom processors aimed at lower power consumption and longer battery life. The Turion Ultra processor was released as part of the "Puma" mobile platform in June 2008.
The Turion X2 Ultra is a dual-core processor to be fabricated on 65 nm technology using 300 mm SOI wafers. It will support DDR2-800 SO-DIMMs and features a DRAM prefetcher to improve performance and a mobile-enhanced northbridge (memory controller, HyperTransport controller, and crossbar switch). Each processor core comes with 1 MiB L2 cache for a total of 2 MiB L2 cache for the entire processor. This is double the L2 cache found on the current Turion 64 X2 processor. Clock rates range from 2.0 GHz to 2.4 GHz, and thermal design power (TDP) will range from 32 watts to 35 watts.
The Turion X2 Ultra processor, unlike earlier Turions, implements three voltage planes: one for the northbridge and one for each core. This, along with multiple phase-locked loops (PLL), allows one core to alter its voltage and operating frequency independently of the other core, and independently of the northbridge. Indeed, in a matter of microseconds, the processor can switch to one of 8 frequency levels and one of 5 voltage levels. By adjusting frequency and voltage during use, the processor can adapt to different workloads and help reduce power consumption. It can operate as low as 250 MHz to conserve power during light use.
Additionally, the processor features deep sleep state C3, deeper sleep state C4 (AltVID), and HyperTransport 3.0 up to 2.6 GHz, or up to 41.6 GB/s bandwidth per link at 16-bit link width and dynamic scaling of HT link width down to 0-bit ("disconnected") in both directions from and to the chipset for four different usage scenarios  . It also implements multiple on-die thermal sensors through integrated SMBUS (SB-TSI) interface (replaces and eliminates the thermal monitor circuit chip through SMBUS in its predecessors) with additional MEMHOT signal sent from embedded controller to the processor, and reduces memory temperature.
Given the above enhancements on the architecture, the cores were minimally modified and are based on the K8 instead of the K10 microarchitecture. AMD Fellow Maurice Steinman has said the cores are almost transistor-for-transistor identical to those found in the 65 nm Turion 64 X2 processors .
Turion II Ultra (codenamed Caspian) is the mobile version of the K10.5 architecture produced using 45 nm fabrication process, also known by its desktop variant Regor. It is a dual core processor, and features clock speeds of 2.4 GHz to 2.7 GHz, 2 MB total L2 cache (1 MB per core), HyperTransport at 3.6 GT/s, and a 128 bit FPU. It maintains a TDP of 35W from its predecessor Turion X2 Ultra (codenamed Griffin).
Turion II is identical to Turion II Ultra, except that the Turion II features only 2 MB of L2 cache (1 MB per core), and higher clock speeds ranging from 2.3 GHz to 2.7 GHz.
The model naming scheme does not make it obvious how to compare one Turion with another, or even an Athlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents a performance rating (PR). The first letter is M for single core processors and T for dual core Turion 64 X2 processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (frugal power consumption). Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 consumes less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.
The release of the Turion II Ultra and Turion II lineups have simplified name methodology; all newly released Turions have the letter "M" followed by a number designating relative performance. The higher the number, the higher the clock speed. For example, the Turion II M500 has a clock speed of 2.2 GHz while the Turion II M520 has a clock speed of 2.3 GHz.
The models support the same features available in Lancaster, plus AMD-V.
|Model number||Frequency||L2 cache||FPU width||HT||Multiplier1||Voltage||TDP||Socket!||Release date||Order part number|
|Turion II P520||2.3 GHz||2 × 1 MB||128-bit||1.8 GHz||11.5×||25 W||Socket S1g4||May 12, 2010||TMP520SGR23GM|
|Turion II P540||2.4 GHz||2 × 1 MB||128-bit||1.8 GHz||12×||25 W||Socket S1g4||October 4, 2010||TMP540SGR23GM|
|Turion II P560||2.5 GHz||2 × 1 MB||128-bit||1.8 GHz||12.5×||25 W||Socket S1g4||October 19, 2010||TMP560SGR23GM|
|Turion II N530||2.5 GHz||2 × 1 MB||128-bit||1.8 GHz||12.5×||35 W||Socket S1g4||May 12, 2010||TMN530DCR23GM|
|Turion II N550||2.6 GHz||2 × 1 MB||128-bit||1.8 GHz||13×||35 W||Socket S1g4||October 4, 2010||TMN550DCR23GM|